The present invention generally relates to a power splitter. More specifically, the present invention relates to an impedance matched active power splitter.
When a system has multiple receivers that operate simultaneously there is a need to have the input signal split among all of the receivers. This should be done with a minimal loss or with amplification to keep a high signal-to-noise ratio (SNR) so that each receive path""s SNR does not suffer. The splitter should be as small as possible and is preferably integrated. The signal range of the split should be as wide as possible to allow for wide band signal applications, such as cable receivers where input signals range from 55 MHz to 860 MHz. Also, the input and output impedances should be matched and the output ports should be isolated from each other.
U.S. Pat. Nos. 6,140,889, 6,118,354, 5,959,507, and 5,347,245 disclose passive power splitter concepts. The splitters disclosed in these patents have power loss with each output having less power than the input. And because they have loss, they effectively increase the noise floor for circuitry that comes after the power split. Also, these splitters need transformers. This reduces the probability for integration, because most radio frequency (RF) applications need ferrite materials to bring the response down to very high frequencies (VHF). In addition, these splitters increase minimum input signal level.
U.S. Pat. No. 5,021,755 discloses another passive power splitter in which transmission lines are used to replace the ferrite baluns. Because of the use of transmission lines, the splitter disclosed in this patent has an added reason for long lines. The line length dictates the lowest frequency to use. The splitter was intended for PC board applications and microwave frequencies. It cannot be integrated for VHF frequencies.
U.S. Pat. Nos. 5,072,199, 4,973,918, and 4,580,114 disclose active power splitter concepts. However, the power splitter disclosed in U.S. Pat. No. 5,072,199 has a topology where the output match and output isolation are enabled by a plurality of output stages, each of which includes a separate source follower field effect transistors (FET) and a single-gate active load FET. On the other hand, U.S. Pat. No. 4,580,114 discloses a topology where the output match comes from reactive filter matching techniques for each output. The output isolation is just that from the reverse isolation of field effect transistors (FETs). Neither the output match nor the output isolation uses feedback techniques. There is no input match. U.S. Pat. No. 4,973,918 is a distributed amp version of U.S. Pat. No. 4,580,114, except this patent discloses the utilization of some distributed amp input matching techniques.
U.S. Pat. No. 5,045,822 discloses the concept of out-of-phase signal cancellation for port-to-port isolation. As disclosed in this patent, the input match circuitry is not part of a feedback path and the signal passes right through it. The input match is composed of a capacitor and an inductor. Further, the splitter disclosed in this patent contains only two output ports. An extension to additional output ports would not work.
FIG. 1 shows an example of a prior art power splitting topology 100. The topology of FIG. 1 comprises a matched amplifier followed by a passive power splitter. A power signal entering at the input port 102 is amplified by the amplifier 104 and split by the 4-way power splitter 106, in two stages, into four output signals. Each output signal arrives at an output port 118a, 118b, 118c and 188d, respectively. The passive power splitter is generally narrow band and large in size. It mainly uses transmission lines and some lumped elements. While it can be made entirely of lumped elements, the number and sizes of the lumped elements make the splitter relatively large rendering the splitter incapable of integration for frequencies lower than approximately 5 GHz.
FIG. 2 shows another example of a prior art power splitting topology 200. The input signal entering the input port 202 is subjected to an impedance transformation network 204. The impedance transformation network 204 prepares the input signal for presentation to a plurality of amplifiers 206a, 206b, 206c, 206d placed in parallel, resulting in the output signal being produced at output ports 208a, 208b, 208c, 208d, respectively. The impedance transformation 204 is provided at the input since the input impedance drops proportionally to the number of amplifiers in parallel. In the example shown in FIG. 2, a transformer is used to perform a 4-to-1 impedance transformation. This splitter is bandwidth-limited and introduces passive losses. It also can be quite large in size, mainly because of the need of the transformer.
The present invention is directed to a 1:N power splitter configured to split an input signal into a number N output signals.
The power splitter""s various components may all reside on a single integrated circuit, preferably using gallium arsenide technology.
In one embodiment, the power splitter of the present invention includes an input node and a number N of output nodes; an input circuit connected between the input node and an intermediate node; N number of amplifying circuits, each connected between the input node and a corresponding one of the N output nodes; and N feedback circuits, each connected between the intermediate node and a corresponding one of the N output nodes.
The input and feedback circuits may comprise passive elements, such as resistors.
The amplifying circuits may be implemented using either field-effect transistors (FETs) or bipolar junction transistors (BJT""s). If the transistor is an FET, it may be a GaAs FET.
Each amplifying circuit may comprise a single transistor. In such case, the input circuit may comprise a resistor having a resistance of R1, each feedback circuit may comprise a resistor having a resistance of R2; each transistor may have a transconductance of GM, a load impedance of RL, and a source impedance of RS; the relationship (NR1+R2+RL)/[N(GMRL+1)]=(NR1+R2+NRS)/(NGMRS+1) may hold. Under some conditions, the relationship R1+RS=GMR2RS may hold, as well.
Each amplifying circuit may comprise first and second transistors cascaded together. In such case, the first transistor of each amplifying circuit may receive an input from the input node, an output of the first transistor may be connected to an input of the second transistor, and the second transistor of each amplifying circuit may have an output connected to a corresponding output node.
In another embodiment, the power splitter of the present invention has an input node, and a number N output nodes. The power splitter also has N number of amplifying circuits, each amplifying circuit connected between the input node and a corresponding one of the N output nodes, and N number of feedback networks, each associated with one of said amplifying circuits. Each feedback network comprises an input circuit connected between the input node and an intermediate node, a feedback circuit connected between said intermediate node and the corresponding one of the N output nodes; and a divider circuit connected between said intermediate node and a common node that is common to all the feedback networks.
In this second embodiment, each input circuit may comprises a resistor with all input circuits having identical resistors, each feedback circuit may comprise a resistor with all feedback circuits having identical resistors, and each third circuit may comprise a resistor with all third circuits having identical resistors.